This founder is teaching chips how to recycle (their energy)

For seven decades, the computing industry has operated under an unshakeable empirical assumption: doing work on silicon means turning electricity into waste heat. As transistor dimensions collapsed toward atomic scales and chip power densities skyrocketed during the artificial intelligence boom, thermal design power (TDP) transitioned from a manageable engineering boundary into the primary wall limiting compute performance. Today’s hyperscale AI workloads do not merely require gigawatts of generation capacity; they demand complex liquid cooling manifolds, chilled water loops, and massive heat-dissipation facilities simply to purge the thermal energy generated when billions of transistors rapidly switch state.

Hannah Earley, the 31-year-old co-founder and Chief Technology Officer of UK-based startup Vaire Computing, argues that this heat generation is not an inevitable law of physics, but a historic artifact of how standard microprocessors were designed. Profiled by MIT Technology Review, Earley and her team are pursuing a radical departure from traditional silicon design: chips built around reversible logic and charge-recovery circuits. Instead of dumping electrical charge into a ground plane—wasting its energy as heat after every clock cycle—Vaire aims to capture, store, and reuse that energy to power subsequent operations, fundamentally challenging the baseline physics of modern microelectronics.

Key Takeaways

• Rethinking Thermal Loss: Vaire Computing, led by CTO Hannah Earley, is commercializing energy-recovering adiabatic design and reversible logic to drastically reduce the heat generated during computation.
• Thermodynamic Boundaries vs. Circuit Reality: While information erasure imposes a theoretical thermodynamic minimum dictated by Landauer’s limit (\(k_BT\ln 2\)), modern conventional CMOS processors dissipate orders of magnitude more energy due to classical charging and switching losses (\(P = \alpha C_{\mathrm{eff}}V_{DD}^{2}f\)).
• The Speed-for-Energy Trade-Off: Adiabatic circuits rely on slowly changing power clocks (\(\tau \gg RC\)) to minimize resistive heat generation, trading high instantaneous switching frequencies for extreme energy efficiency.
• The System-Level Benchmark: Reversible computing cannot be judged purely on gate-level energy recovery. The true test lies in total system energy per workload at matched throughput, factoring in compiler-driven "uncomputation" state tracking, clock generator losses, and static leakage currents.

What Happened?

The technological narrative surrounding semiconductor progress has traditionally focused on scaling node dimensions: shrinking gate lengths from nanometers down to angstroms to cram more switches onto a piece of silicon. However, as Dennard scaling collapsed in the mid-2000s and voltage scaling hit a floor set by thermal noise, pushing higher clock frequencies caused power consumption to explode. In modern data centers, this power wall has created a multi-billion-dollar infrastructure crisis. A significant portion of the electricity fed into a computing facility is converted almost instantly into ambient heat, requiring additional energy to pump that thermal load out of the facility.

According to reporting by MIT Technology Review, Hannah Earley’s approach at Vaire Computing steps outside the conventional CMOS paradigm. Rather than treating heat management as an external mechanical problem—solved with bigger heat sinks, microfluidic channels, or phase-change cooling—Earley approaches energy dissipation as a logic design flaw. Vaire is building prototype processors designed to recover electrical charge before it dissipates into heat, routing that charge back into the power network to perform the next computational operation.

Vaire Computing, operating across Cambridge and London, has attracted early-stage venture capital interest by positioning its technology at the intersection of mathematical logic and low-power hardware architecture. Earley, who completed her doctoral work exploring unconventional computing paradigms, asserts that by coordinating the precise movement of charge and pairing it with reversible logic architectures, silicon chips can operate at a fraction of the thermal footprint of traditional state-of-the-art processors.

This development arrives at a critical juncture for the tech sector. As processing clusters scaled for large language models and real-time inference eat up double-digit percentages of regional power grids, the demand for non-traditional chip architectures has reached an all-time high. Compute density is no longer constrained solely by how many transistors fit on a reticle-sized die, but by how much heat can be extracted from that die without causing structural decay, timing faults, or catastrophic thermal runaway.

The Technology Behind It

The engineering idea behind “recycling” computational energy is not harvesting waste heat after it forms, but avoiding some of its generation through reversible logic and charge recovery. Two distinct limits matter. Logically irreversible operations—such as overwriting an unknown bit—discard information and, under standard thermodynamic assumptions, require at least \(k_BT\ln 2\) of dissipation per erased bit: approximately \(2.9\times10^{-21}\) joules at 300 K. Conventional CMOS operates far above that bound, with dynamic power approximately \(P=\alpha C_{\mathrm{eff}}V_{DD}^{2}f\), plus leakage and short-circuit losses. Consequently, most present-day dissipation is not directly dictated by Landauer’s limit; it arises from how circuits move charge. The supplied technical disclosures from Vaire do not disclose its specific implementation, so its specific circuitry and performance cannot be inferred from the headline alone.

In ordinary CMOS, charging a capacitance \(C\) from a fixed-voltage supply draws \(CV^2\): half becomes stored electrostatic energy and half is dissipated in the charging path. Discharging conventionally then dissipates the stored half. Adiabatic circuits instead use a slowly varying “power clock,” keeping the voltage drop across conducting switches small and subsequently returning stored charge to the power-clock network. For an idealized linear ramp of duration \(\tau\), resistive loss scales approximately as \(E_{\mathrm{loss}}\sim(RC/\tau)CV^2\), assuming \(\tau\gg RC\). This exchanges switching speed for lower dissipation rather than producing free computation. Resonant clock networks can circulate energy between capacitance and inductance, but finite quality factor \(Q\) introduces a loss of approximately \(2\pi E_{\mathrm{stored}}/Q\) per cycle; switches, clock drivers, distribution wiring, and voltage conversion add further overhead.

Logical reversibility is a separate architectural requirement, not an automatic consequence of using an energy-recovering clock. A reversible machine preserves enough state that each transition has a unique predecessor. An irreversible function \(f(x)\) can be embedded in a reversible mapping such as \((x,y)\mapsto(x,y\oplus f(x))\), but intermediate results cannot simply be discarded. Reversible execution commonly computes a result, copies its classical bit pattern into a retained output register, and runs the computation backward to clear temporary state—“uncomputation.” That creates substantial compiler and microarchitecture work: reversible instruction sequences, temporary-storage allocation, scheduling, and time–space tradeoffs. Conventional caches, speculative execution, register overwrites, and memory interfaces are not automatically compatible with this discipline. Partial charge recovery can still be useful without a fully reversible processor, but it does not eliminate the thermodynamic cost of information erasure.

The decisive silicon metric is therefore system energy per useful completed workload at matched throughput and reliability, not a gate-level recovery percentage. Slower transitions reduce resistive losses but increase leakage energy per operation, roughly \(E_{\mathrm{leak}}\approx VI_{\mathrm{leak}}\tau\), yielding a finite optimum rather than unlimited improvement from slowing down. Larger circuits and additional execution steps can consume the savings; interconnect resistance, parasitic capacitance, phase alignment, process variation, and clock loading constrain scaling. A convincing demonstration would measure net energy drawn at external supply rails, including power-clock generation, memory, I/O, state cleanup, and control, against an appropriately optimized CMOS baseline. The opportunity is genuine if recoverable switching energy dominates those costs; the headline alone does not establish that Vaire has crossed that system-level threshold.

Why It Matters & Industry Impact

If energy recovery and reversible computing can be successfully commercialized at scale, the implications for the technology sector would be profound. Current data center expansions across North America, Europe, and Asia are facing immediate constraints, constrained not by capital expenditures or server rack availability, but by localized power grid capacities. As seen in recent reporting on the surging power footprint of AI clusters, computing facilities are demanding dedicated power infrastructure, pushing municipal utilities to their operational margins.

For cloud hyperscalers like Microsoft, Amazon Web Services, and Google, an architecture that slashes active power dissipation without requiring sub-kelvin cryogenic environments could radically shift unit economics. Lower thermal generation reduces the physical footprint of server clusters by minimizing the spacing required between server blades, eliminating bulky air-ducting infrastructure, and lowering cooling-water consumption. It also allows chips to operate at higher functional density without triggering aggressive thermal throttling.

Beyond data center clusters, energy-recovering silicon holds significant promise for edge computing, wearable health monitors, and autonomous systems. Devices constrained by localized battery capacity—such as biomedical implants, remote sensor arrays, or smart eyewear—could operate far longer on a single charge if internal processing dissipates negligible dynamic power. The broader industry, currently watching energy storage breakthroughs and grid infrastructure struggle to keep pace with demand, views hardware-level energy reduction as an essential parallel track.

However, the transition from conventional microprocessors to adiabatic logic presents steep barriers for modern software development. Modern computer engineering relies on decades of abstraction layers, optimized compilers, speculative hardware execution, and cache hierarchy designs that explicitly rely on overwriting registers at high speeds. Embracing reversible logic forces a full-stack redesign: compilers must map classical algorithms into reversible mappings, manage memory uncomputation without blowing up memory footprints, and balance temporal execution against thermal efficiency.

What Experts & Sources Say

The core physics behind reversible computation date back decades to pioneering theoretical work by Rolf Landauer and Charles Bennett at IBM Research, as well as Edward Fredkin and Tommaso Toffoli. These physicists proved that computation itself is not inherently dissipative; only the loss or erasure of information generates entropy. While the theoretical framework is sound, veteran chip designers remain cautious about the engineering hurdles of bringing adiabatic silicon to market.

Independent semiconductor analysts point out that while charge-recovery principles have been validated in research settings and niche ultra-low-power ASICs, scaling them to complex, highly parallel computing structures is notoriously difficult. Resonant clocking networks demand extraordinarily precise inductance-capacitance balancing across varying workloads. If an AI workload exhibits dynamic variations in execution paths, maintaining the exact clock frequency required for high dynamic quality factor (\(Q\)) circuit resonance becomes a formidable control problem.

Furthermore, chip architects emphasize the challenge of static leakage current. In deep-submicron processes (e.g., 3nm and 2nm nodes), gate-oxide tunneling and subthreshold leakage account for a massive share of total power draw. Because adiabatic systems deliberately extend signal transition times (\(\tau\)) to lower dynamic resistive losses, they lengthen the duration over which switches sit in intermediate voltage states, potentially expanding static leakage energy (\(E_{\mathrm{leak}} \approx V I_{\mathrm{leak}} \tau\)). Balancing dynamic energy recovery against static leakage penalties requires bespoke silicon formulation and material optimization.

What Happens Next?

Over the next 6 to 12 months, the semiconductor industry will be watching Vaire Computing for tangible silicon validation. Up to this point, much of the discourse around energy-recycling start-ups has focused on mathematical modeling, circuit simulation, and small-scale field-programmable gate array (FPGA) proofs-of-concept. To establish credibility among tier-one system integrators, Vaire must tape out physical test chips on commercial foundry nodes and demonstrate verified, system-level power numbers.

The primary benchmark of success will be a clear demonstration of net power savings measured directly at the external power rails of a complete evaluation board. This measurement must account for the power consumption of the external clock generation circuitry, memory access buses, input/output (I/O) drivers, and the logic overhead required to handle uncomputation. Showing energy savings solely at the gate level without accounting for driving overhead will not satisfy enterprise hardware architects.

In parallel, Vaire and any peers in the unconventional hardware ecosystem must develop robust software development kits (SDKs) and compiler toolchains. Software developers will not hand-code reversible assembly instructions. Success hinges on automated translation engines that take high-level tensor operations or classical code bases and translate them into optimized, reversible execution graphs. This dynamic mirrors software challenges seen elsewhere in advanced computing, where algorithmic optimizations dictate whether radical underlying hardware can actually execute effectively in real-world environments.

Bigger Picture

The industry's engagement with Hannah Earley’s work highlights a broader realization in computer engineering: the era of "easy" performance gains through traditional transistor scaling is drawing to a close. For decades, chipmakers relied on shrinking gate lengths to deliver faster clock speeds within stable power envelopes. As physical limitations have stalled that trajectory, hardware designers are forced to re-examine long-discarded concepts from theoretical physics, including optical computing, neuromorphic designs, and adiabatic reversible logic.

Energy-recycling architecture represents a structural shift in how engineers conceptualize information processing. Instead of treating computation as a destructive process where electricity flows through a resistor and disappears forever into a thermal sink, computing is re-imagined as a non-destructive manipulation of state, where energy shuttles smoothly back and forth between functional units.

If startup ventures like Vaire Computing successfully clear the engineering hurdles of system-level overhead, static leakage, and compiler design, they could fundamentally alter the trajectory of high-performance hardware. Even a partial deployment—using charge-recovery circuits for specialized memory buses or repetitive tensor arithmetic blocks—could dramatically lower the energy barrier for modern artificial intelligence, turning computational efficiency from an environmental liability into a sustainable, scalable asset.

Frequently Asked Questions

What is energy-recycling or adiabatic computing?

Energy-recycling or adiabatic computing is a circuit design strategy that minimizes energy loss by slowing down logic state transitions and using charge-recovery clock networks. Rather than quickly dumping electrical charge to ground after a circuit switches state (which converts the charge to waste heat), adiabatic circuits return the charge back to a power clock or resonant circuit to be reused in subsequent operations.

How does reversible logic differ from traditional chip architecture?

Traditional computer architecture uses irreversible logic gates, where input information cannot be reconstructed from the output (for example, an standard AND gate produces an output of 0, but you cannot determine which of the three possible input pairs produced it). Erasing that input state dissipates a fundamental minimum amount of energy known as Landauer’s limit. Reversible logic, by contrast, maps inputs to outputs in a 1-to-1 preserved state, allowing the system to execute operations backward ("uncomputation") to clear intermediate data without logically erasing information.

Can reversible computing chips directly replace existing GPUs and CPUs?

Not immediately. Reversible computing requires a fundamentally different microarchitecture, memory execution model, and compiler infrastructure. While an adiabatic chip could theoretically be integrated into a system as a specialized accelerator for specific mathematical or AI workloads, standard software programs written for conventional x86 or ARM architectures must be recompiled and restructured to run natively on a reversible instruction set environment.